The invention relates generally to semiconductor structures and fabrication of semiconductor chips and, in particular, to the fabrication of field effect transistors (FETs) in bulk silicon (Si) substrates. More particularly, aspects of the invention relate to fabrication of junction gate FETs (JFETs) and metal-semiconductor field effect transistors (MESFETs) with self-aligned double gates on and/or in bulk Si substrates.
In fabricating dual-gate FETs, it can be difficult to ensure proper alignment of the gates. As a result, fabrication yield can suffer, increasing costs and time to delivery. Further, conventional dual-gate FETs, typically formed as junction gate FETs (JFETs), can have excessive gate-drain and/or gate-source capacitances, which can increase power consumption and/or threshold voltage of the FET.